1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection device, and more particularly to an ESD protection device having reduced trigger voltage and improved second breakdown current characteristic.
2. Description of the Prior Art
Electrostatic discharge (ESD) in semiconductor integrated circuits (IC”s) is a well-known problem. The inadvertent presence of a sudden voltage spike in an integrated circuit can cause physical destruction of circuit features. For example, ESD-induced spikes can rupture the thin gate oxide of a field effect transistor (FET), or simply degrade the p-n junction of a semiconductor device, effectively destroying proper IC operation. A typical “gate oxide” in a MOS transistor will rupture when its dielectric strength is more than approximately 107 V/cm.
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a partial plan view showing a prior art ESD device 10. FIG. 2 is a cross-sectional view of the prior art ESD device 10 taken along section A—A of FIG. 1. As shown in FIG. 1 and FIG. 2, the prior art ESD device 10 comprises fingers including two NMOS transistors 11 and 12 formed on a P type semiconductor substrate 20. The NMOS transistor 11 comprises an N+ doped region 132, an N-type lightly-doped drain (hereinafter referred to as “NLDD”) region 141 extended from the N+ doped region 132 to the polysilicon gate 112, an N+ doped region 134, an NLDD region 142 extended from the N+ doped region 134 to the polysilicon gate 112, a P channel 151 defined between the NLDD regions 141 and 142, a gate dielectric layer 111 formed between the substrate 20 and the gate 112, and spacers 113 on sidewalls of the gate 112. NMOS transistor 12 comprises the N+ doped region 134, an NLDD region 143 extended from the N+ doped region 134 to the polysilicon gate 122, an N+ doped region 136, an NLDD region 144 extended from the N+ doped region 136 to the polysilicon gate 122, a P channel 152 defined between the NLDD regions 143 and 144, a gate dielectric layer 121 formed between the substrate 20 and the gate 122, and spacers 123 on sidewalls of the gate 122.
As seen in FIG. 1, a plurality of metal contacts 162, 164, and 166 are distributed on the N+ doped regions 132, 134, and 136, respectively, for connecting signals. When operating the above-described NMOS based ESD device, by way of example, the metal contacts 162 and 166 are connected to ground or Vss, the metal contacts 164 are connected to the input/output (I/O) terminal, the semiconductor substrate 20 is grounded.
However, the operation performance of the above-described ESD device 10 is not satisfactory, for example, overhigh trigger voltage and inferior second breakdown current characteristic. It is desired to reduce the trigger voltage of the ESD device for well protection of integrated circuit. One approach to reduce the above-described NMOS based ESD device is applying so-called “Zener implant”. As shown in FIG. 3, P type dopants are implanted deep into the substrate 20 to form a Zener implant region underneath the N+ doped region 134. However, this approach is not effective in PMOS based ESD device. Furthermore, the prior art Zener implant method needs an additional photo mask, thus not cost-effective.